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TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 1 the lumenology company copyright 2011, taos inc. www.taosinc.com 256 1 sensor-element organization 400 dots-per-inch (dpi) sensor pitch high linearity and uniformity wide dynamic range . . . 4000:1 (72 db) output referenced to ground low image lag ... 0.5% typ operation to 8 mhz single 3-v to 5-v supply rail-to-rail output swing (ao) no external load resistor required replacement for tsl1402 description the TSL1402R linear sensor array consists of two sections of 128 photodiodes each and associated charge amplifier circuitry, aligned to form a contiguous 256 1 pixel array. the device incorporates a pixel data-hold function that provides simultaneous integration start and stop times for all pixels. the pixels measure 63.5 m by 55.5 m, with 63.5-m center-to-center spacing and 8- m spacing between pixels. operation is simplified by internal logic requiring only a serial-input pulse (si) and a clock. the TSL1402R is intended for use in a wide variety of applications including mark and code reading, ocr and contact imaging, edge detection and positioning, and optical encoding. functional block diagram (each section ? pin numbers apply to section 1) 2 3 si clk 128-bit shift register q128 switch control logic integrator reset _ + pixel 1 pixel 2 pixel 128 pixel 3 sample/hold/ output analog bus q3 q2 q1 hold so 13 output buffer gain trim v dd ao gnd 5 4 1 s1 s2 2 1 3 1 2 texas advanced optoelectronic solutions inc. 1001 klein road suite 300 plano, tx 75074 (972) 673-0759 (top view) nc ? no internal connection ? ? ? ? ? v dd 1 si1 2 clk 3 ao1 4 gnd 5 so2 6 nc 7 14 nc 13 so1 12 gnd 11 nc 10 si2 9 nc 8 ao2 ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 2 copyright 2011, taos inc. the lumenology company www.taosinc.com terminal functions terminal description name no. description ao1 4 analog output of section 1. ao2 8 analog output of section 2. clk 3 clock. clk controls charge transfer, pixel output, and reset. gnd 5,12 ground (substrate). all voltages are referenced to gnd. nc 7, 9, 11, 14 no internal connection. si1 2 serial input (section 1). si1 defines the start of the data-out sequence for section 1. si2 10 serial input (section 2). si2 defines the start of the data-out sequence for section 2. so1 13 serial output (section 1). so1 provides a signal to drive the si2 input (in serial connection). so2 6 serial output (section 2). so2 provides a signal to drive the si input of another device for cascading or as an end-of-data indication. v dd 1 supply voltage. supply voltage for both analog and digital circuitry. detailed description device operation (assumes serial connection) the sensor consists of 256 photodiodes, called pixels, arranged in a linear array. light energy impinging on a pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that pixel. during the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. the amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. the output and reset of the integrators is controlled by a 256-bit shift register and reset logic. an output cycle is initiated by clocking in a logic 1 on si1. an internal signal, called hold, is generated from the rising edge of si1 and simultaneously transmitted to sections 1 and 2. this causes all 256 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. as the si pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output ao. simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19 th clock. on the 128 th clock rising edge, the si pulse is clocked out on the so1 pin (section 1) and becomes the si pulse for section 2 (si2). the rising edge of the 129 th clock cycle terminates the so1 pulse, and returns the analog output ao1 of section 1 to high-impedance state. analog output ao2 now becomes the active output. as in section 2, so2 is clocked out on the 256 th clock pulse. note that a 257 th clock pulse is needed to terminate the so2 pulse and return ao2 to the high-impedance state. if a minimum integration time is desired, the next si pulse may be presented after a minimum delay of t qt (pixel charge transfer time) after the 257 th clock pulse. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 3 the lumenology company copyright 2011, taos inc. www.taosinc.com ao is an op amp-type output that does not require an external pull-down resistor. this design allows a rail-to-rail output vo ltage swing. with v dd = 5 v, the output is nominally 0 v for no light input, 2 v for normal white level, and 4.8 v for saturation light level. when the device is not in the output phase, ao is in a high-impedance state. the voltage developed at analog output (ao) is given by: v out = v drk + (r e ) (e e )(t int ) where: v out is the analog output voltage for white condition v drk is the analog output voltage for dark condition r e is the device responsivity for a given wavelength of light given in v/( j/cm 2 ) e e is the incident irradiance in w/cm 2 t int is integration time in seconds the TSL1402R can be connected in the serial mode, where it takes 256 clocks to read out all pixels, or in the parallel mode where it takes 128 clocks to read out all pixels (see application information and figures 9 and 10). a 0.1 f bypass capacitor should be connected between v dd and ground as close as possible to the device. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 4 copyright 2011, taos inc. the lumenology company www.taosinc.com absolute maximum ratings ? supply voltage range, v dd ?0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ?0.3 v to v dd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) or (v i > v dd ) ?20 ma to 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v dd ) ?25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high impedance or power-off state, v o ?0.3 v to v dd + 0.3 v . . . continuous output current, i o (v o = 0 to v dd ) ?25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v dd or gnd ?40 ma to 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog output current range, i o ?25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum light exposure at 638 nm 5 mj/cm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a ?25 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?25 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see figure 1 and figure 2) min nom max unit supply voltage, v dd 3 5 5.5 v input voltage, v i 0 v dd v high-level input voltage, v ih 2 v dd v low-level input voltage, v il 0 0.8 v wavelength of light source, 400 1000 nm clock frequency, f clock 5 8000 khz sensor integration time, parallel, t int (see note 1) 0.03375 100 ms sensor integration time, serial, t int (see note 1) 0.04975 100 ms setup time, serial input, t su(si) 20 ns hold time, serial input, t h(si) (see note 2) 0 ns operating free-air temperature, t a 0 70 c notes: 1. integration time is calculated as follows: t int(min) = (256 ? 18) clock period + 20 s where 256 is the number of pixels in series, 18 is the required logic setup clocks, and 20 s is the pixel charge transfer time (t qt ) 2. si must go low before the rising edge of the next clock pulse. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 5 the lumenology company copyright 2011, taos inc. www.taosinc.com electrical characteristics at f clock = 1 mhz, v dd = 5 v, t a = 25 c, p = 640 nm, t int = 5 ms, r l = 330 , e e = 11 w/cm 2 (unless otherwise noted) (see note 3) parameter test conditions min typ max unit v out analog output voltage (white, average over 256 pixels) see note 4 1.6 2 2.4 v v drk analog output voltage (dark, average over 256 pixels) e e = 0 0 0.1 0.2 v prnu pixel response nonuniformity see note 5 10% nonlinearity of analog output voltage see note 6 0.4% output noise voltage see note 7 1 mvrms r e responsivity see note 8 25 35 45 v/ ( j/cm 2 ) v analog output saturation voltage v dd = 5 v, r l = 330 4.5 4.8 v v sat analog output saturation voltage v dd = 3 v, r l = 330 2.5 2.8 v se saturation exposure v dd = 5 v, see note 9 136 nj/cm 2 se saturation exposure v dd = 3 v, see note 9 78 nj/cm 2 dsnu dark signal nonuniformity all pixels, e e = 0, see note 10 0.04 0.12 v il image lag see note 11 0.5% i supply current v dd = 5 v, e e = 0 6 9 ma i dd supply current v dd = 3 v, e e = 0 5 8 ma i ih high-level input current v i = v dd 10 a i il low-level input current v i = 0 10 a c i input capacitance, si 5 pf c i input capacitance, clk 10 pf notes: 3. all measurements made with a 0.1 f capacitor connected between v dd and ground. 4. the array is uniformly illuminated with a diffused led source having a peak wavelength of 640 nm. 5. prnu is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of th e device under test when the array is uniformly illuminated at the white irradiance level. prnu includes dsnu. 6. nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. rms noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. r e(min) = [v out(min) ? v drk(max) ] (e e t int ) 9. se(min) = [v sat(min) ? v drk(min) ] ? e e t int ) [v out(max) ? v drk(min) ] 10. dsnu is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. image lag is a residual signal left in a pixel from a previous exposure. it is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: il v out (il) v drk v out (white) v drk 100 timing requirements (see figure 1 and figure 2) min nom max unit t su(si) setup time, serial input (see note 12) 20 ns t h(si) hold time, serial input (see note 12 and note 13) 0 ns t w pulse duration, clock high or low 50 ns t r , t f input transition (rise and fall) time 0 500 ns t qt pixel charge transfer time 20 s notes: 12. input pulses have the following characteristics: t r = 6 ns, t f = 6 ns. 13. si must go low before the rising edge of the next clock pulse. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 6 copyright 2011, taos inc. the lumenology company www.taosinc.com dynamic characteristics over recommended ranges of supply voltage and operating free-air temperature (see figures 7 and 8) parameter test conditions min typ max unit t s analog output settling time to 1% r l = 330 , c l = 10 pf 120 ns t pd(so) propagation delay time, so1, so2 50 ns typical characteristics ???????????????????? ???????????????????? ???????? ???????? 18 clock cycles 257 clock cycles clk si ao internal reset integration hi-z hi-z not integrating integrating t int t qt figure 1. timing waveforms (serial connection) 50% ao si clk pixel 128 (256) t s 0 v 0 v 5 v t h(si) 5 v t su(si) t w 1 (129) 2 128 129 (257) pixel 1 (129) t pd(so) t pd(so) so figure 2. operational waveforms (each section) ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 7 the lumenology company copyright 2011, taos inc. www.taosinc.com typical characteristics 0.4 0 300 500 700 900 0.6 0.8 photodiode spectral responsivity 0.2 ? wavelength ? nm normalized responsivity t a = 25 c 1 1100 400 600 800 1000 figure 3 figure 4 normalized idle supply current vs free-air temperature t a ? free-air temperature ? c 010 3040 70 60 i dd ? normalized idle supply current 0 0.5 1 1.5 2 20 50 figure 5 white output voltage vs free-air temperature t a ? free-air temperature ? c 0 0.5 1 1.5 2 v out ? output voltage ? v 010 3040 70 60 20 50 v dd = 5 v t int = 0.5 ms to 15 ms figure 6 dark output voltage vs free-air temperature t a ? free-air temperature ? c 0.06 0.08 0.10 v out ? output voltage 010 3040 70 60 20 50 v dd = 5 v t int = 15 ms t int = 5 ms t int = 2.5 ms t int = 0.5 ms t int = 1 ms 0.07 0.09 ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 8 copyright 2011, taos inc. the lumenology company www.taosinc.com typical characteristics figure 7 settling time vs. load r l ? load resistance ? settling time to 1% ? ns 0 200 400 600 800 1000 0 100 200 300 400 500 600 v dd = 3 v v out = 1 v 470 pf 220 pf 100 pf 10 pf figure 8 settling time vs. load r l ? load resistance ? settling time to 1% ? ns 0 200 400 600 800 1000 0 100 200 300 400 500 600 v dd = 5 v v out = 1 v 470 pf 220 pf 100 pf 10 pf ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 9 the lumenology company copyright 2011, taos inc. www.taosinc.com application information power supply considerations for optimum device performance, power-supply lines should be decoupled by a 0.01- f to 0.1-f capacitor with short leads mounted close to the device package (see figure 9 and figure 10). connection diagrams 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v dd si1 clk ao1 gnd so2 nc nc so1 gnd nc si2 nc ao2 si clk ao v dd 0.1 f TSL1402R figure 9. serial connection 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v dd si1 clk ao1 gnd so2 nc nc so1 gnd nc si2 nc ao2 si clk v dd 0.1 f TSL1402R ao1 (pixels 1 ? 128) ao2 (pixels 129 ? 256) figure 10. parallel connection ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 10 copyright 2011, taos inc. the lumenology company www.taosinc.com application information integration time the integration time of the linear array is the period during which light is sampled and charge accumulates on each pixel?s integrating capacitor. the flexibility to adjust the integration period is a powerful and useful feature of the taos tsl14xx linear array family. by changing the integration time, a desired output voltage can be obtained on the output pin while avoiding saturation for a wide range of light levels. the integration time is the time between the si (start integration) positive pulse and the hold positive pulse minus the 18 setup clocks. the tsl14xx linear array is normally configured with the si and hold pins tied together. this configuration will be assumed unless otherwise noted. sending a high pulse to si (observing timing rules for setup and hold to clock edge) starts a new cycle of pixel output and integration setup. however, a minimum of ( n +1) clocks, where n is the number of pixels, must occur before the next high pulse is applied to si. it is not necessary to send si immediately on/after the ( n +1) clocks. a wait time adding up to a maximum total of 100 ms between si pulses can be added to increase the integration time creating a higher output voltage in low light applications. each pixel of the linear array consists of a light-sensitive photodiode. the photodiode converts light intensity to a voltage. the voltage is sampled on the sampling capacitor by closing switch s2 (position 1) (see the functional block diagram on page 1). logic controls the resetting of the integrating capacitor to zero by closing switch s1 (position 2). at si input, all of the pixel voltages are simultaneously scanned and held by moving s2 to position 2 for all pixels. during this event, s2 for pixel 1 is in position 3. this makes the voltage of pixel 1 available on the analog output. on the next clock, s2 for pixel 1 is put into position 2 and s2 for pixel 2 is put into position 3 so that the voltage of pixel 2 is available on the output. following the si pulse and the next 17 clocks after the si pulse is applied, the s1 switch for all pixels remains in position 2 to reset (zero out) the integrating capacitor so that it is ready to begin the next integration cycle. on the rising edge of the 19 th clock, the s1 switch for all the pixels is put into position 1 and all of the pixels begin a new integration cycle. the first 18 pixel voltages are output during the time the integrating capacitor is being reset. on the 19 th clock following an si pulse, pixels 1 through 18 have switch s2 in position 1 so that the sampling capacitor can begin storing charge. for the period from the 19 th clock through the n th clock, s2 is put into position 3 to read the output voltage during the n th clock. on the next clock the previous pixel s2 switch is put into position 1 to start sampling the integrating capacitor voltage. for example, s2 for pixel 19 moves to position 1 on the 20 th clock. on the n +1 clock, the s2 switch for the last ( n th ) pixel is put into position 1 and the output goes to a high-impedance state. if a si was initiated on the n +1 clock, there would be no time for the sampling capacitor of pixel n to charge to the voltage level of the integrating capacitor. the minimum time needed to guarantee the sampling capacitor for pixel n will charge to the voltage level of the integrating capacitor is the charge transfer time of 20 s. therefore, after n +1 clocks, an extra 20 s wait must occur before the next si pulse to start a new integration and output cycle. the minimum integration time for any given array is determined by time required to clock out all the pixels in the array and the time to discharge the pixels. the time required to discharge the pixels is a constant. therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels in the array. a slower clock speed increases the minimum integration time and reduces the maximum light level for saturation on the output. the minimum integration time shown in this data sheet is based on the maximum clock frequency of 8 mhz. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 11 the lumenology company copyright 2011, taos inc. www.taosinc.com application information the minimum integration time can be calculated from the equation: t int(min) 1 maximum clock frequency ( n 18) pixels 20 s where: n is the number of pixels in the case of the TSL1402R with the maximum clock frequency of 8 mhz, the minimum integration time would be: t int(min) 0.125 s (128 18) 20 s 33.75 s it is good practice on initial power up to run the clock ( n +1) times after the first si pulse to clock out indeterminate data from power up. after that, the si pulse is valid from the time following ( n +1) clocks. the output will go into a high-impedance state after the n +1 high clock edge. it is good practice to leave the clock in a low state when inactive because the si pulse required to start a new cycle is a low-to-high transition. the integration time chosen is valid as long as it falls in the range between the minimum and maximum limits for integration time. if the amount of light incident on the array during a given integration period produces a saturated output (max voltage output), then the data is not accurate. if this occurs, the integration period should be reduced until the analog output voltage for each pixel falls below the saturation level. the goal of reducing the period of time the light sampling window is active is to lower the output voltage level to prevent saturation. however, the integration time must still be greater than or equal to the minimum integration period. if the light intensity produces an output below desired signal levels, the output voltage level can be increased by increasing the integration period provided that the maximum integration time is not exceeded. the maximum integration time is lim ited by the length of time the integrating capacitors on the pixels can hold their accumulated charge. the maximum integration time should not exceed 100 ms for accurate measurements. it should be noted that the data from the light sampled during one integration period is made available on the analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock period. in other words, at any given time, two groups of data are being handled by the linear array: the previous measured light data is clocked out as the next light sample is being integrated. although the linear array is capable of running over a wide range of operating frequencies up to a maximum of 8 mhz, the speed of the a/d converter used in the application is likely to be the limiter for the maximum clock frequency. the voltage output is available for the whole period of the clock, so the setup and hold times required for the analog-to-digital conversion must be less than the clock period. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 12 copyright 2011, taos inc. the lumenology company www.taosinc.com mechanical information this assembly consists of 2 sensor chips mounted on a printed-circuit board in a clear molded plastic package. top of die to top of package ?????? ??????????? 1234567 14 13 12 11 10 9 8 ?????? top view side view bottom view 14 4.60 min 14 0.508 0.406 end view 1.90 0.76 7.87 7.37 2 2.16 1.42 0.89 1.29 14 0.50 0.00 3.18 2.79 0.53 0.28 pin 1 indicator 19.30 18.29 12 2.54 nonaccumulative see note b 10.67 9.65 sensors c l 3.62 3.92 sensors to pin 1 pixel 1 to pin 1 notes: a. all linear dimensions are in millimeters. b. the true-position spacing is 2.54 mm between lead centerlines. each pin centerline is located within 0.25 mm of its true longitudinal positions. c. index of refraction of clear plastic is 1.52. d. the gap between the individual sensor dies in the array is 57 m typical (51 m minimum and 75 m maximum). e. this drawing is subject to change without notice. figure 11. packaging configuration ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 13 the lumenology company copyright 2011, taos inc. www.taosinc.com mechanical information 64.00 55.50 8.00 63.50 76.50 46.00 95.50 37.00 154.50 13.00 11.00 25.50 14.50 theoretical pixel layout for ideal continuous die actual multi-die pixel layout for die-to-die edge joining n ?2 n ?1 n 12 n ?2 n ?1 n 12 note b note c 3 3 notes: a. all linear dimensions are in micrometers. b. spacing between outside pixels of adjacent die is typical. c. die-to-die spacing. d. this drawing is subject to change without notice. figure 12. edge pixel layout dimensions ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 14 copyright 2011, taos inc. the lumenology company www.taosinc.com soldering information tsl1402 256 1 linear array 14-lead gold pin package soldering instructions: the TSL1402R has been designed to withstand a lead temperature during soldering of 260 c for 10 seconds at a distance of 1.6 mm from the package body. in most applications, these through-hole parts will be sufficiently protected by the combination of the pcb or flex plus the standoff provided by the package. if lead clipping is required, this should be performed after solder attach to prevent the pulling of the lead from the package body. as in all board manufacturing, care should be taken to prevent part bending during board singulation or final assembly. if the process includes both surface-mount parts and the TSL1402R, the surface mount operations should be completed first with the through-hole parts afterward. these parts can be washed as a part of the flux cleanup operation. a final top-surface cleanup may be required with water or alcohol to remove any remaining particles. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 15 the lumenology company copyright 2011, taos inc. www.taosinc.com production data ? information in this document is current at publication date. products conform to specifications in accordance with the terms of texas advanced optoelectronic solutions, inc. standard warranty. production processing does not necessarily include testing of all parameters. notice texas advanced optoelectronic solutions, inc. (t aos) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. customers are advised to contact taos to obtain the latest product information before placing orders or designing taos products into systems. taos assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. taos further makes no claim as to the suitability of its products for any particu lar purpose, nor does taos assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. texas advanced optoelectronic solutions, inc. products are not designed or intended for use in critical applications in which the failure or malfunction of the taos product may result in personal injury or death. use of t aos products in life support systems is expressly unauthorized and any such use by a customer is completely at the customer?s risk. lumenology, taos, the taos logo, and texas advanced optoelectronic solutions are registered trademarks of texas advanced optoelectronic solutions incorporated. ams ag technical content still valid
TSL1402R 256 1 linear sensor array with hold taos041g ? november 2011 16 copyright 2011, taos inc. the lumenology company www.taosinc.com ams ag technical content still valid

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